Benchmarks / Hardware design and debugging

Hardware design and debugging

Fix and verify RTL hardware designs (Verilog, SystemVerilog, Chisel) in real chip repositories.

Part of Architecture and engineering.

• HWE-Benchby Peking UniversityTask level · Resolved rate

  79.9%GPT-5.6 Sol max (Codex CLI) · 31 Jul 2026

  Strong